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STA506A
45V 4A QUAD POWER HALF BRIDGE
PRODUCT PREVIEW
1

FEATURES
MULTIPOWER BCD TECHNOLOGY MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION 200m RdsON COMPLEMENTARY DMOS OUTPUT STAGE CMOS COMPATIBLE LOGIC INPUTS THERMAL PROTECTION THERMAL WARNING OUTPUT UNDER VOLTAGE PROTECTION SHORT CIRCUIT PROTECTION
Figure 1. Package
PowerSO36
Table 1. Order Codes
Part Number STA506A Package Power SO36 (Slug Up)

bridge (Binary mode) with half current capability. The device is particularly designed to make the output stage of a stereo All-Digital High Efficiency (DDXTM) amplifier capable to deliver 60 + 60W @ THD = 10% at Vcc 32V output power on 8 load and 80W @ THD = 10% at VCC 36V on 8 load in single BTL configuration. In single BTL configuration is also capable to deliver a peak of 120W @THD = 10% at VCC = 32V on 4 load. The input pins have threshold proportional to VL pin voltage.
2
DESCRIPTION
STA506A is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half Figure 2. Application Circuit (Dual BTL)
VCC1A IN1A IN1A +3.3V VL CONFIG PWRDN R57 10K R59 10K C58 100nF TH_WAR IN1B VDD VDD VSS VSS C58 100nF C53 100nF C60 100nF IN2A VCCSIGN VCCSIGN IN2A GND-Reg GND-Clean 21 22 33 34 M17 35 8 9 36 31 20 19 M16 M15 REGULATORS 7 VCC2A C32 1F OUT2A OUT2A 6 GND2A PWRDN FAULT 23 24 25 27 26 TRI-STATE PROTECTIONS & LOGIC M5 28 30 M4 13 M2 29 M3 15 17 16 C30 1F OUT1A OUT1A 14 GND1A C52 330pF
+VCC C55 1000F
L18 22H C20 100nF R98 6 C99 100nF C23 470nF C101 100nF
8
12
VCC1B C31 1F OUT1B OUT1B GND1B R63 20 R100 6 C21 100nF L19 22H
11 10
TH_WAR IN1B
L113 22H C110 100nF C109 330pF R103 6 R104 20
4
VCC2B C33 1F OUT2B OUT2B
R102 6 C111 100nF
3 2
C107 100nF C108 470nF C106 100nF
8
IN2B
IN2B GNDSUB
32 M14
L112 22H
1
5
GND2B
D00AU1148B
November 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
REV. 2 1/14
STA506A
Table 2. Pin Function
Pin n. 1 2;3 4 5 6 7 8;9 10 ; 11 12 13 14 15 16 ; 17 18 19 20 21 ; 22 23 24 25 26 27 28 29 30 31 32 33 ; 34 35 ; 36 Pin Name GND-SUB OUT2B VCC 2B GND2B GND2A VCC 2A OUT2A OUT1B VCC1B GND1B GND1A VCC1A OUT1A NC GND-clean GND-reg Vdd VL CONFIG PWRDN TRI-STATE FAULT TH-WAR IN1A IN1B IN2A IN2B VSS VCC Sign Substrate Ground Output Half Bridge 2B Positive Supply Negative Supply Negative Supply Positive Supply Output Half Bridge 2A Output Half Bridge 1B Positive Supply Negative Supply Negative Supply Positive Supply Output Half Bridge 1A Not Connected Logical Ground Ground for regulator Vdd 5V Regulator Referred to Ground Logic Reference Voltage Configuration pin Stand-by pin High-Z pin Fault pin Advisor Thermal Warning Advisor Input of Half Bridge 1A Input of Half Bridge 1B Input of Half Bridge 2A Input of Half Bridge 2B 5V Regulator Referred to +VCC Signal Positive Supply Description
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STA506A
Table 3. Functional Pin Status
Pin name FAULT FAULT (*) TRI-STATE TRI-STATE PWRDN PWRDN THWAR THWAR(*) CONFIG CONFIG(**)
(*) : (**):
Pin n. 27 27 26 26 25 25 28 28 24 24
Logical value 0 1 0 1 0 1 0 1 0 1
IC -STATUS Fault detected (Short circuit, or Thermal ..) Normal Operation All powers in Hi-Z state Normal operation Low absorpion Normal operation Temperature of the IC =130C Normal operation Normal Operation OUT1A = OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B)
The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) to implement single BTL (mono mode) operation for high current.
Figure 3. Pin Connection
VCCSign VCCSign VSS VSS IN2B IN2A IN1B IN1A TH_WAR FAULT TRI-STATE PWRDN CONFIG VL VDD VDD GND-Reg GND-Clean
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
D01AU1273
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND-SUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C.
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STA506A
Table 4. Absolute Maximum Ratings
Symbol VCC Vmax Ptot Top Tstg, Tj Parameter DC Supply Voltage (Pin 4,7,12,15) Maximum Voltage on pins 23 to 32 (logic reference) Power Dissipation (Tcase = 70C) Operating Temperature Range Storage and Junction Temperature Value 45 5.5 50 0 to 70 -40 to 150 Unit V V W C C
Table 5. (*) Recommended Operating Conditions
Symbol VCC VL Tamb DC Supply Voltage Input Logic Reference Ambient Temperature Parameter Min. 10 2.7 0 3.3 Typ. Max. 40 5.0 70 Unit V v C
(*) Performances not guaranteed beyond recommended Operating Conditions
Table 6. Thermal Data
Symbol Tj-case TjSD Twarn thSD Parameter Thermal Resistance Junction to Case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis 150 130 25 Min. Typ. Max. 1.5 Unit C/W C C C
Table 7. Electrical Characteristcs: refer to circuit in Fig.1 (VL = 3.3V; VCC = 32V; RL = 8; fsw = 384KHz; Tamb = 25C unless otherwise specified)
Symbol RdsON Idss gN gP Dt_s Dt_d td ON td OFF tr tf VCC VIN-H Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Id=1A VCC =35V 95 95 10 20 50 100 100 25 25 10 40 VL/2 +300mV Test conditions Min. Typ. 200 Max. 270 50 Unit m A % % ns ns ns ns ns ns V V
Power Pchannel RdsON Matching Id=1A Power Nchannel RdsON Matching Low current Dead Time (static) Id=1A see test circuit no.1; see fig. 3
High current Dead Time (dinamic) L=22H; C = 470nF; RL = 8 Id=3.5A; see fig. 5 Turn-on delay time Turn-off delay time Rise time Fall time Supply voltage operating voltage High level input voltage Resistive load Resistive load Resistive load; as fig.3 Resistive load; as fig. 3
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STA506A
Table 7. (continued)
Symbol VIN-L IIN-H IIN-L Parameter Low level input voltage Hi level Input current Low level input current Pin Voltage = VL Pin Voltage = 0.3V VL = 3.3V 0.8 1.7 3 Test conditions Min. VL/2 300mV 1 1 35 Typ. Max. Unit V A A A V V mA
IPWRDN-H Hi level PWRDN pin input current VLOW VHIGH IVCCPWRDN IFAULT
Low logical state voltage VLow VL = 3.3V (pin PWRDN, TRISTATE) (note 1) High logical state voltage VHigh VL = 3.3V (pin PWRDN, TRISTATE) (note 1) Supply CURRENT from Vcc in Power Down Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Supply Current from Vcc in Tristate Supply Current from Vcc in operation both channel switching) Isc (short circuit current limit) (note 2) Undervoltage protection threshold Output minimum pulse width No Load PWRDN = 0
Vpin = 3.3V VCC = 30V; Tri-state = 0 VCC =30V; Input Pulse width = 50% Duty; Switching Frequency = 384KHz; No LC filters; 4
1 22 50
mA mA mA
IVCC-hiz IVCC
IVCC-q VUV tpw_min
6 7
8
A V
70
150
ns
Notes: 1. The following table explains the VLOW, VHIGH variation with VL
Table 8.
VL 2.7 3.3 5 VLOW min 0.7 0.8 0.85 VHIGH max 1.5 1.7 1.85 Unit V V V
Note 2: see relevant Application Note AN1994
Table 9. Logic Truth Table (see fig. 4)
TRI-STATE 0 1 1 1 1 INxA x 0 0 1 1 INxB x 0 1 0 1 Q1 OFF OFF OFF ON ON Q2 OFF OFF ON OFF ON Q3 OFF ON ON OFF OFF Q4 OFF ON OFF ON OFF OUTPUT MODE Hi-Z DUMP NEGATIVE POSITIVE Not used
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STA506A
Figure 4. Test Circuit.
OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50%
M58
DTr OUTxY
M57
DTf
INxY
R 8
+ -
V67 = vdc = Vcc/2
D03AU1458
gnd
Figure 5.
+VCC
Q1 INxA OUTxA
Q2 OUTxB INxB
Q3
Q4
GND
D00AU1134
Figure 6.
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B
DTout(A) M58 Q1 OUTA Rload=8 L67 22 C69 470nF DTout(B) L68 22 C70 470nF Q2 OUTB M64
DTin(A) INA
DTin(B) INB
Iout=4A M57 Q3
Iout=4A Q4 M63
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
D03AU1517
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STA506A
3
TECHNICAL INFO:
The STA506A is a dual channel H-Bridge that is able to deliver more than 60W per channel (@ THD=10%) of audio output power in high efficiency. The STA506A converts both DDX and binary-controlled PWM signals into audio power at the load. It includes a logic interface , integrated bridge drivers, high efficiency MOSFET outputs and thermal and short circuit protection circuitry. In DDX mode, two logic level signals per channel are used to control high-speed MOSFET switches to connect the speaker load to the input supply or to ground in a Bridge configuration, according to the damped ternary Modulation operation. In Binary Mode operation , both Full Bridge and Half Bridge Modes are supported. The STA506A includes overcurrent and thermal protection as well as an under-voltage Lockout with automatic recovery if FAULT and TRISTATE pins are connected together to an external capacitor, as in fig.9 Figure 7. STA506A Block Diagram Full-Bridge DDX(R) or Binary Modes
IN1A/B IN2A/B VL PWRDN TRI-STATE OUT1A
Logic I/F and Decode
Left H-Bridge
OUT1B
FAULT TWARN
Protection Circuitry Regulators
OUT2A
Right H-Bridge
OUT2B
Figure 8. STA506A Block Diagram Binary Half-Bridge Mode
IN1A/B IN2A/B VL PWRDN TRI-STATE
Logic I/F and Decode
LeftA -Bridge LeftB -Bridge RightA -Bridge RightB -Bridge
OUT1A
OUT2A
FAULT TWARN
Protection Circuitry Regulators
OUT1B
OUT2B
3.1 Logic Interface and Decode: The STA506A power outputs are controlled using one or two logic level timing signals. In order to provide a proper logic interface, the VL input must operate at the dame voltage as the DDX control logic supply. 3.2 Protection Circuitry: The STA506A includes protection circuitry for over-current and thermal overload conditions. A thermal warning pin (pin.28) is activated low (open drain MOSFET) when the IC temperature exceeds 130C, in advance of the thermal shutdown protection. When a fault condition is detected , an internal fault signal acts to immediately disable the output power MOSFETs, placing both H-Bridges in high impedance state. At the same time an opendrain MOSFET connected to the fault pin (pin.27) is switched on.
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STA506A
There are two possible modes subsequent to activating a fault: - 1) SHUTDOWN mode: with FAULT (pull-up resistor) and TRI-STATE pins independent, an activated fault will disable the device, signaling low at the FAULT output. The device may subsequently be reset to normal operation by toggling the TRI-STATE pin from High to Low to High using an external logic signal. - 2) AUTOMATIC recovery mode: This is shown in the Application Circuit of fig.1. The FAULT and TRI-STATE pins are shorted together and connected to a time constant circuit comprising R59 and C58. An activated FAULT will force a reset on the TRI-STATE pin causing normal operation to resume following a delay determined by the time constant of the circuit. If the fault condition is still present , the circuit operation will continue repeating until the fault condition is removed . An increase in the time constant of the circuit will produce a longer recovery interval. Care must be taken in the overall system design as not to exceed the protection thesholds under normal operation. 3.3 Power Outputs: The STA506A power and output pins are duplicated to provide a low impedance path for the device's bridged outputs . All duplicate power, ground and output pins must be connected for proper operation. The PWRDN or TRI-STATE pins should be used to set all MOSFETS to the Hi-Z state during power-up until the logic power supply, VL , is settled. 3.4 Parallel Output / High Current Operation: When using DDX Mode output , the STA506A outputs can be connected in parallel in order to increase the output current capability to a load. In this configuration the STA506A can provide 80W into 8 ohm or up to 120W into 4ohm. This mode of operation is enabled with the CONFIG pin (pin.24) connected to Vdd and the inputs combined IN1A=IN1B, IN2A=IN2B and the outputs combined OUT1A=OUT1B, OUT2A=OUT2B. 3.5 Additional Informations: Output Filter: A passive 2nd-order passive filter is used on the STA506A power outputs to reconstruct an analog Audio Signal . System performance can be significantly affected by the output filter design and choice of passive components. A filter design for 6ohm/8ohm loads is shown in the Typical Application circuit of fig.1. Figure 9 shows a filter design suitable for 4ohm loads. Figure 10 shows a filter for 1/2 bridge mode , 4 ohm loads. 3.6 Power Dissipation & Heat Sink Requirements: The power dissipated within the device will depend primarily on the supply voltage, load impedance and output modulation level. The PowerSO36 package of the STA506A includes an exposed thermal slug on the top of the device to provide a direct thermal path from the IC to the heatsink. Careful consideration must be given to the overall thermal design . See figure 8 for power derating versus Slug temperature using different heatsinks and considering the Rth-jc =1.5C/W.
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STA506A
Figure 9. STA506A Power Derating Curve
Pdiss(W)
60 50 40 30 20 10 0 0 20 40 60 80 100 120 140 160
4 2 3 1
1 -Infinite 2- 1.5C/W 3- 3 C/W 4- 4 C/W
Slug temperature C
Figure 10. Typical Single BTL Configurationto Obtain 120W @ THD 10%, RL= 4, VCC = 32V (note 1))
+3.3V 100nF
VL GND-Clean GND-Reg 10K 100nF X7R VDD VDD CONFIG
23
18 17 16 11 10
N.C. 10H OUT1A OUT1A OUT1B OUT1B OUT2A 22 1/2W 6.2 1/2W 6.2 1/2W
19 20
100nF FILM 100nF X7R 470nF FILM 100nF X7R 100nF FILM 10H
21 22 24 28 25 27 26
4
9 8
OUT2A OUT2B
330pF
TH_WAR nPWRDN 10K
TH_WAR PWRDN FAULT TRI-STATE 100nF IN1A IN1B IN2A IN2B VSS VSS 100nF X7R 100nF X7R Add. VCCSIGN VCCSIGN GNDSUB
3 2
OUT2B
15
VCC1A 1F X7R 2200F 63V
32V
29 30 31 32 33 34
12
VCC1B VCC2A
IN1A
7
32V 1F X7R
IN1B
4 14
VCC2B GND1A GND1B
35
13 GND2A
36 1
6 GND2B 5
D03AU1514
Note: 1. "A PWM modulator as driver is needed . In particular, this result is performed using the STA30X+STA50X demo board". Peak Power for t 1sec
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STA506A
Figure 11. Typical Quad Half Bridge Configuration
VCC1P IN1A IN1A +3.3V VL CONFIG PWRDN R57 10K R59 10K C58 100nF TH_WAR IN1B VDD VDD VSS VSS C58 100nF C53 100nF C60 100nF IN2A VCCSIGN VCCSIGN IN2A GND-Reg GND-Clean 21 22 33 34 M17 35 8 9 36 31 20 19 M16 M15 OUTPR OUTPR 6 PGND2P R43 20 C43 330pF L13 22H C73 100nF R53 6 C83 100nF R66 5K REGULATORS 7 VCC2P PWRDN FAULT 23 24 25 27 26 TRI-STATE PROTECTIONS & LOGIC M5 28 30 M4 13 M2 29 M3 15 17 16 OUTPL OUTPL 14 PGND1P R41 20 C41 330pF L11 22H C71 100nF R51 6 C81 100nF R62 5K R61 5K
+VCC C21 2200F
C31 820F
C91 1F
4
12
VCC1N C51 1F OUTNL OUTNL PGND1N C61 100nF L12 22H R42 20 C42 330pF C72 100nF R52 6 C82 100nF R64 5K
11 10
TH_WAR IN1B
R63 5K
C32 820F
C92 1F
4
R65 5K
C33 820F
C93 1F
4
4
VCC2N C52 1F OUTNR OUTNR C62 100nF L14 22H R44 20 C44 330pF C74 100nF R54 6 C84 100nF R68 5K
3 2
IN2B
R67 5K
C34 820F
IN2B GNDSUB
32 M14
1
5
PGND2N
C94 1F
4
D03AU1474
For more information refer to the application notes AN1456 and AN1661
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STA506A
Figure 12. THD+N vs Frequency
1
T
Figure 15. THD+N vs Output Power
THD(% 10 ) 5
0.5
Vcc=32V Rl=8ohm
2 1 0.5
Vcc=36V Rl=8ohm
0.2
F=1KHz
%
0.1
0.2
0.05
0.1 0.05
0.02
0.02
0.01 20 50 100 200 500 1k 2k 5k 10k 20k
0.01 100m
200m
500m
1
2 Pout(W )
5
10
20
50 80
Hz
Figure 13. Output Power vs Vsupply
Po(W 80 )
70
Table 10. THD+N vs Output Power
THD(% 10 ) 5
Rl=8ohm
60 50 40 30 20 10
0.02
F=1KHz
2
THD=10%
Vcc=32V Rl=8ohm
1 0.5
F=1KHz
0.2 0.1
TH D=1%
0.05
+14
+16
+18
+20
+22
+24
+26
+28
+30
+32
+34 +36
0.01 100m 200m 500m 1 2 Pout(W ) 5 10 20 50 80
Vsupply(V)
Figure 14. THD+N vs Output Power
THD(% ) 10 5
2 1 0.5
Vcc=34V Rl=8ohm F=1KHz
0.2 0.1 0.05
0.02 0.01 100m
200m
500m
1
2 Pout(W )
5
10
20
50 80
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STA506A
Figure 16. Power SO36 (Slug Up) Mechanical Data & Package Dimensions
DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s mm TYP. inch TYP.
MIN. 3.25 3.1 0.8 0.030 0.22 0.23 15.8 9.4
MAX. 3.43 3.2 1 -0.040 0.38 0.32 16 9.8
MIN. 0.128 0.122 0.031 0.0011 0.008 0.009 0.622 0.37
MAX. 0.135 0.126 0.039 -0.0015 0.015 0.012 0.630 0.38
OUTLINE AND MECHANICAL DATA
0.2
0.008
1 13.9 10.9 5.8 2.9 0.65 11.05 0 15.5 0.8 0.075 15.9 1.1 1.1 10 8 0 0.61 0.031 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.228 0.114
0.039 0.57 0.437 0.114 0.244 1.259 0.026 0.435 0.003 0.625 0.043 0.043 10 8
PowerSO36 (SLUG UP)
(1) "D and E1" do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006") (2) No intrusion allowed inwards the leads.
7183931 D
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STA506A
Table 11. Revision History
Date August 2004 November 2004 Revision 1 2 First Issue Changed Vcc from 9 min to 10 min Description of Changes
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STA506A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners DDX is a trademark of Apogee tecnology inc. (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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